An introduction to logic circuit testing
An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level und...
| Main Author: | |
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| Format: | Electronic |
| Language: | English |
| Published: |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
Morgan & Claypool Publishers,
c2009.
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| Series: | Synthesis lectures on digital circuits and systems (Online) ;
# 17. |
| Subjects: | |
| Online Access: | View fulltext via EzAccess |
Table of Contents:
- Introduction
- Faults in logic circuits
- Stuck-at fault
- Bridging faults
- Delay fault
- Breaks and transistors stuck-open and stuck-on or stuck-open faults in CMOS
- Breaks
- Stuck-on and stuck-open faults
- Basic concepts of fault detection
- Controllability and observability
- Undetectable faults
- Equivalent faults
- Temporary faults
- References
- Fault detection in logic circuits
- Test generation for combinational logic circuits
- Truth table and fault matrix
- Path sensitization
- D-algorithm
- PODEM
- FAN
- Delay fault detection
- Testing of sequential circuits
- Designing checking experiments
- Test generation using the circuit structure and the state table
- References
- Design for testability
- Ad hoc techniques
- Scan-path technique for testable sequential circuit design
- Level-sensitive scan design
- Clocked hazard-free latches
- Double-latch and single-latch LSSD
- Random access scan technique
- Partial scan
- Testable sequential circuit design using nonscan techniques
- Crosscheck
- Boundary scan
- References
- Built-in self-test
- Test pattern generation for BIST
- Exhaustive testing
- Pseudoexhaustive pattern generation
- Pseudorandom pattern generator
- Deterministic testing
- Output response analysis
- Transition count
- Syndrome checking
- Signature analysis
- BIST architectures
- Built-in logic block observer
- Self-testing using an MISR and parallel shift register sequence generator
- LSSD on-chip self-test.