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An introduction to logic circuit testing

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level und...

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Bibliographic Details
Main Author: Lala, Parag K., 1948-
Format: Electronic
Language:English
Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009.
Series:Synthesis lectures on digital circuits and systems (Online) ; # 17.
Subjects:
Logic circuits > Testing.
Digital electronics > Testing.
Integrated circuits > Very large scale integration > Testing.
Online Access:View fulltext via EzAccess
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020 # # |a 9781598293517 (electronic bk.) 
020 # # |a 9781598293500 (pbk.) 
024 7 # |a 10.2200/S00149ED1V01Y200808DCS017  |2 doi 
035 # # |a 265419385 (OCLC) 
035 # # |a (CaBNvSL)gtp00532198 
040 # # |a CaBNvSL  |c CaBNvSL  |d CaBNvSL 
050 # 4 |a TK7868.L6  |b L255 2009 
082 0 4 |a 621.395  |2 22 
100 1 # |a Lala, Parag K.,  |d 1948- 
245 1 3 |a An introduction to logic circuit testing  |c Parag K. Lala.  |h [electronic resource] / 
260 # # |a San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :  |b Morgan & Claypool Publishers,  |c c2009. 
300 # # |a 1 electronic text (x, 99 p. : ill.) :  |b digital file. 
490 1 # |a Synthesis lectures on digital circuits and systems,  |v # 17  |x 1932-3174 ; 
500 # # |a Part of: Synthesis digital library of engineering and computer science. 
500 # # |a Title from PDF t.p. (viewed on December 3, 2008). 
500 # # |a Series from website. 
504 # # |a Includes bibliographical references. 
505 0 # |a Introduction -- Faults in logic circuits -- Stuck-at fault -- Bridging faults -- Delay fault -- Breaks and transistors stuck-open and stuck-on or stuck-open faults in CMOS -- Breaks -- Stuck-on and stuck-open faults -- Basic concepts of fault detection -- Controllability and observability -- Undetectable faults -- Equivalent faults -- Temporary faults -- References -- Fault detection in logic circuits -- Test generation for combinational logic circuits -- Truth table and fault matrix -- Path sensitization -- D-algorithm -- PODEM -- FAN -- Delay fault detection -- Testing of sequential circuits -- Designing checking experiments -- Test generation using the circuit structure and the state table -- References -- Design for testability -- Ad hoc techniques -- Scan-path technique for testable sequential circuit design -- Level-sensitive scan design -- Clocked hazard-free latches -- Double-latch and single-latch LSSD -- Random access scan technique -- Partial scan -- Testable sequential circuit design using nonscan techniques -- Crosscheck -- Boundary scan -- References -- Built-in self-test -- Test pattern generation for BIST -- Exhaustive testing -- Pseudoexhaustive pattern generation -- Pseudorandom pattern generator -- Deterministic testing -- Output response analysis -- Transition count -- Syndrome checking -- Signature analysis -- BIST architectures -- Built-in logic block observer -- Self-testing using an MISR and parallel shift register sequence generator -- LSSD on-chip self-test. 
506 # # |a Abstract freely available; full-text restricted to subscribers or individual document purchasers. 
510 0 # |a Compendex 
510 0 # |a INSPEC 
510 0 # |a Google scholar 
510 0 # |a Google book search 
520 # # |a An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. 
530 # # |a Also available in print. 
538 # # |a Mode of access: World Wide Web. 
538 # # |a System requirements: Adobe Acrobat reader. 
650 # 0 |a Logic circuits  |x Testing. 
650 # 0 |a Digital electronics  |x Testing. 
650 # 0 |a Integrated circuits  |x Very large scale integration  |x Testing. 
690 # # |a Digital circuits. 
690 # # |a Logic circuit testing. 
690 # # |a VLSI. 
690 # # |a Fault detection. 
690 # # |a Design-for-testability. 
690 # # |a Response evaluation techniques. 
690 # # |a BIST. 
690 # # |a D-Algorithm. 
690 # # |a PODEM. 
690 # # |a FAN. 
690 # # |a LFSR. 
730 0 # |a Synthesis digital library of engineering and computer science. 
830 # 0 |a Synthesis lectures on digital circuits and systems (Online) ;  |v # 17. 
856 4 2 |u https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.2200/S00149ED1V01Y200808DCS017  |z View fulltext via EzAccess 

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