An introduction to logic circuit testing

• Main Author: Lala, Parag K., 1948-
• Format: Electronic
• Language: English
• Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009.
• Series: Synthesis lectures on digital circuits and systems (Online) ; # 17.
• Subjects: Logic circuits > Testing.; Digital electronics > Testing.; Integrated circuits > Very large scale integration > Testing.
• Online Access: View fulltext via EzAccess
• Item Description: Part of: Synthesis digital library of engineering and computer science.; Title from PDF t.p. (viewed on December 3, 2008).; Series from website.
• Physical Description: 1 electronic text (x, 99 p. : ill.) : digital file.; Also available in print.
• Format: Mode of access: World Wide Web.; System requirements: Adobe Acrobat reader.
• Bibliography: Includes bibliographical references.
• ISBN: 9781598293517 (electronic bk.); 9781598293500 (pbk.)
• ISSN: 1932-3174
• Access: Abstract freely available; full-text restricted to subscribers or individual document purchasers.

An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips.