Introduction to logic synthesis using Verilog HDL

• Main Author: Reese, Robert B. 1958-
• Other Authors: Thornton, Mitchell Aaron.
• Format: Electronic
• Language: English
• Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2006.
• Edition: 1st ed.
• Series: Synthesis lectures on digital circuits and systems (Online) ; #6.
• Subjects: Logic design > Computer programs.; Verilog (Computer hardware description language); Electronic digital computers > Design and construction.; Computer hardware description languages.
• Online Access: Abstract with links to full text

Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and...

Table of Contents:

• Digital logic review with Verilog quickstart
• Learning objectives
• Logic synthesis introduction and motivation
• Combinational logic in Verilog
• Assign statements
• Always procedural blocks
• Combinational building blocks in Verilog
• Multibit/multiinput muxes, Verilog hierarchical design and bus notation
• Addition, subtraction
• Multiplication, division
• Shifting
• Tri-state logic
• Sequential logic in Verilog
• One-bit storage elements
• DFF chains
• Asynchronous versus synchronous inputs
• Registers, counters, and shift registers
• Event-driven simulation and Verilog
• Event-driven simulation basics
• Timing considerations
• Presynthesis versus postsynthesis simulation
• Blocking versus nonblocking assignments and synthesis
• Verilog coding guidelines
• Summary
• Synchronous sequential circuit design
• Learning objectives
• Sequential circuits
• Sequential circuit motivation
• Synchronizing signals: the clock
• Synchronous sequential circuit architectures
• Contents
• Models of finite state machines
• Basics of algorithmic state machine (ASM) charts
• The ASM chart model and an example controller
• The state diagram model
• State assignment
• Low-level models of controllers
• State equations
• State tables
• Controller circuit analysis
• Mealy and Moore machine conversion
• Mealy to Moore machine conversion
• Moore to Mealy conversion
• State machine equivalence
• Verilog descriptions of synchronous sequential circuits
• Example Verilog descriptions
• Verilog descriptions for the Mealy machine model of an example controller
• Verilog descriptions for the Moore machine model of an example controller
• Summary
• Biography.