Introduction to logic synthesis using Verilog HDL

• Main Author: Reese, Robert B. 1958-
• Other Authors: Thornton, Mitchell Aaron.
• Format: Electronic
• Language: English
• Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2006.
• Edition: 1st ed.
• Series: Synthesis lectures on digital circuits and systems (Online) ; #6.
• Subjects: Logic design > Computer programs.; Verilog (Computer hardware description language); Electronic digital computers > Design and construction.; Computer hardware description languages.
• Online Access: Abstract with links to full text
• Item Description: Part of: Synthesis digital library of engineering and computer science.; Series from website.; Title from PDF t.p. (viewed on October 11, 2008).
• Physical Description: 1 electronic text (vii, 75 p. : ill.) : digital file.; Also available in print.
• Format: Mode of access: World Wide Web.; System requirements: Adobe Acrobat Reader.
• Bibliography: Includes bibliographical references (p. 73).
• ISBN: 1598291076 (electronic bk.); 9781598291070 (electronic bk.); 1598291068 (pbk.); 9781598291063 (pbk.)
• ISSN: 1932-3174
• Access: Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and progress to synchronous sequential logic systems. Common pitfalls in the development of synthesizable Verilog HDL are also discussed along with methods for avoiding them. The target audience is any one with a basic understanding of digital logic principles who wishes to learn how to model digital systems in the Verilog HDL in a manner that also allows for automatic synthesis. A wide range of readers, from hobbyists and undergraduate students to seasoned professionals, will find this a compelling and approachable work. This book provides concise coverage of the material and includes many examples, enabling readers to quickly generate high-quality synthesizable Verilog models.