Introduction to logic synthesis using Verilog HDL
Introduction to Logic Synthesis Using Verilog HDL explains how to write accurate Verilog descriptions of digital systems that can be synthesized into digital system net lists with desirable characteristics. The book contains numerous Verilog examples that begin with simple combinational networks and...
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| Format: | Electronic |
| Language: | English |
| Published: |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
Morgan & Claypool Publishers,
c2006.
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| Edition: | 1st ed. |
| Series: | Synthesis lectures on digital circuits and systems (Online) ;
#6. |
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| Online Access: | Abstract with links to full text |