Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...
| Main Authors: | , |
|---|---|
| Corporate Author: | |
| Format: | Electronic |
| Language: | English |
| Published: |
Boston, MA :
Springer US,
1996.
|
| Subjects: | |
| Online Access: | View fulltext via EzAccess |