Logic Synthesis and Verification Algorithms

Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis...

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Bibliographic Details
Main Authors: Hachtel, Gary D. (Author), Somenzi, Fabio. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic
Language:English
Published: Boston, MA : Springer US, 1996.
Subjects:
Online Access:View fulltext via EzAccess
LEADER 03210nam a22005415i 4500
001 22975
003 DE-He213
005 20151204155237.0
007 cr nn 008mamaa
008 100301s1996 xxu| s |||| 0|eng d
020 # # |a 9780306475924  |9 978-0-306-47592-4 
024 7 # |a 10.1007/b117060  |2 doi 
050 # 4 |a TK7888.4 
072 # 7 |a TJFC  |2 bicssc 
072 # 7 |a TEC008010  |2 bisacsh 
082 0 4 |a 621.3815  |2 23 
100 1 # |a Hachtel, Gary D.  |e author. 
245 1 0 |a Logic Synthesis and Verification Algorithms  |c by Gary D. Hachtel, Fabio Somenzi.  |h [electronic resource] / 
264 # 1 |a Boston, MA :  |b Springer US,  |c 1996. 
300 # # |a XXXII, 564 p.  |b online resource. 
336 # # |a text  |b txt  |2 rdacontent 
337 # # |a computer  |b c  |2 rdamedia 
338 # # |a online resource  |b cr  |2 rdacarrier 
347 # # |a text file  |b PDF  |2 rda 
505 0 # |a A Quick Tour of Logic Synthesis with the Help of a Simple Example -- Two Level Logic Synthesis -- Boolean Algebras -- Synthesis of Two-Level Circuits -- Heuristic Minimization of Two-level Circuits -- Binary Decision Diagrams (BDDs) -- Models of Sequential Systems -- Models of Sequential Systems -- Synthesis and Verification of Finite State Machines -- Finite Automata -- Multilevel Logic Synthesis -- Multi-Level Logic Synthesis -- Multi-Level Minimization -- Automatic Test Generation for Combinational Circuits -- Technology Mapping. 
520 # # |a Logic Synthesis and Verification Algorithms is a textbook designed for courses on VLSI Logic Synthesis and Verification, Design Automation, CAD and advanced level discrete mathematics. It also serves as a basic reference work in design automation for both professionals and students. Logic Synthesis and Verification Algorithms is about the theoretical underpinnings of VLSI (Very Large Scale Integrated Circuits). It combines and integrates modern developments in logic synthesis and formal verification with the more traditional matter of Switching and Finite Automata Theory. The book also provides background material on Boolean algebra and discrete mathematics. A unique feature of this text is the large collection of solved problems. Throughout the text the algorithms covered are the subject of one or more problems based on the use of available synthesis programs. 
650 # 0 |a Engineering. 
650 # 0 |a Computer logic. 
650 # 0 |a Computer science  |x Mathematics. 
650 # 0 |a Computers. 
650 # 0 |a Computer-aided engineering. 
650 # 0 |a Electrical engineering. 
650 # 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Logics and Meanings of Programs. 
650 2 4 |a Electrical Engineering. 
650 2 4 |a Computer-Aided Engineering (CAD, CAE) and Design. 
650 2 4 |a Discrete Mathematics in Computer Science. 
650 2 4 |a Computing Methodologies. 
700 1 # |a Somenzi, Fabio.  |e author. 
710 2 # |a SpringerLink (Online service) 
773 0 # |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9780792397465 
856 4 0 |u https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/b117060  |z View fulltext via EzAccess 
912 # # |a ZDB-2-ENG 
912 # # |a ZDB-2-BAE 
950 # # |a Engineering (Springer-11647)