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Design and test technology for dependable systems-on-chip

Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).

Bibliographic Details
Corporate Author: IGI Global.
Other Authors: Ubar, Raimund, 1941-, Raik, Jaan, 1972-, Vierhaus, Heinrich Theodor, 1951-
Format: Electronic
Language:English
Published: Hershey, Pa. : IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), c2011.
Subjects:
Systems on a chip > Design and construction.
Networks on a chip > Design and construction.
Systems on a chip > Testing.
Networks on a chip > Testing.
Built-in self repair for logic structures
Combined test-data compression and test planning
Diagnostic modeling of digital systems
Fault simulation and fault injection technology
Fault-tolerant and fail-safe design based on reconfiguration
Flexible fault-tolerant schedules for embedded systems
Memory testing and self-repair
Optimizing fault tolerance for multi-processor system-on-chip
Software-based self-test of embedded microprocessors
Transient faults detection and compensation
Online Access:Chapter PDFs via platform:

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