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Design and test technology for dependable systems-on-chip

Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC).

Bibliographic Details
Corporate Author: IGI Global.
Other Authors: Ubar, Raimund, 1941-, Raik, Jaan, 1972-, Vierhaus, Heinrich Theodor, 1951-
Format: Electronic
Language:English
Published: Hershey, Pa. : IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA), c2011.
Subjects:
Systems on a chip > Design and construction.
Networks on a chip > Design and construction.
Systems on a chip > Testing.
Networks on a chip > Testing.
Built-in self repair for logic structures
Combined test-data compression and test planning
Diagnostic modeling of digital systems
Fault simulation and fault injection technology
Fault-tolerant and fail-safe design based on reconfiguration
Flexible fault-tolerant schedules for embedded systems
Memory testing and self-repair
Optimizing fault tolerance for multi-processor system-on-chip
Software-based self-test of embedded microprocessors
Transient faults detection and compensation
Online Access:Chapter PDFs via platform:
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020 # # |a 9781609602147 (ebook) 
020 # # |z 9781609602123 (hardcover) 
020 # # |z 1609602129 (hardcover) 
024 7 # |a 10.4018/978-1-60960-212-3  |2 doi 
035 # # |a (CaBNVSL)gtp00546193 
035 # # |a (OCoLC)707616682 
040 # # |a CaBNVSL  |c CaBNVSL  |d CaBNVSL 
050 # 4 |a TK7895.E42  |b D467 2011e 
082 0 4 |a 621.3815  |2 22 
245 0 0 |a Design and test technology for dependable systems-on-chip  |c Raimund Ubar, Jaan Raik, and Heinrich Theodor Vierhaus, editors.  |h [electronic resource] / 
260 # # |a Hershey, Pa. :  |b IGI Global (701 E. Chocolate Avenue, Hershey, Pennsylvania, 17033, USA),  |c c2011. 
300 # # |a electronic texts (1 v.) :  |b digital files. 
504 # # |a Includes bibliographical references. 
505 0 # |a 1. System-level design of NoC-based dependable embedded systems / Mihkel Tagel, Peeter Ellervee, Gert Jervan -- 2. Synthesis of flexible fault-tolerant schedules for embedded systems with soft and hard timing constraints / Viacheslav Izosimov ... et al. -- 3. Optimizing fault tolerance for multi-processor system-on-chip / Dimitar Nikolov ... et al. -- 4. Diagnostic modeling of digital systems with multi-level decision diagrams / Raimund Ubar ... et al. -- 5. Enhanced formal verification flow for circuits integrating debugging and coverage analysis / Daniel Grosse, Görschwin Fey, Rolf Drechsler -- 6. Advanced technologies for transient faults detection and compensation / Matteo Reorda, Luca Sterpone, Massimo Violante -- 7. Memory testing and self-repair / Mária Fischerová, Elena Gramatová -- 8. Fault-tolerant and fail-safe design based on reconfiguration / Hana Kubatova, Pavel Kubalik -- 9. Self-repair technology for global interconnects on SoCs / Daniel Scheit, Heinrich Vierhaus -- 10. Built-in self repair for logic structures / Tobias Koal, Heinrich Vierhaus -- 
505 0 # |a 11. Self-repair by program reconfiguration in VLIW processor architectures / Mario Schölzel, Pawel Pawlowski, Adam Dabrowski -- 12. Fault simulation and fault injection technology based on SystemC / Silvio Misera, Roberto Urban -- 13. High-level decision diagram simulation for diagnosis and soft-error analysis / Jaan Raik ... et al. -- 14. High-speed logic level fault simulation / Raimund Ubar, Sergei Devadze -- 15. Software-based self-test of embedded microprocessors / Paolo Bernardi ... et al. -- 16. SoC self test based on a test-processor / Tobial Koal, Rene Kothe, Heinrich Vierhaus -- 17. Delay faults testing / Marcel Baláž, Roland Dobai, Elena Gramatová -- 18. Low power testing / Zdenek Kotásek, Jaroslav Škarvada -- 19. Thermal-aware SoC test scheduling / Zhiyuan He, Zebo Peng, Petru Eles -- 20. Study on combined test-data compression and test planning for testing of modular SoCs / Anders Larsson ... et al. -- 21. Reduction of the transferred test data amount / Ondrej Novák -- 22. Sequential test set compaction in LFSR reseeding / Artur Jutman, Igor Aleksejev, Jaan Raik. 
506 # # |a Restricted to subscribers or individual electronic text purchasers. 
520 3 # |a Covers aspects of system design and efficient modelling, and also introduces various fault models and fault mechanisms associated with digital circuits integrated into System on Chip (SoC), Multi-Processor System-on Chip (MPSoC) or Network on Chip (NoC). 
530 # # |a Also available in print. 
538 # # |a Mode of access: World Wide Web. 
588 # # |a Description based on title screen (IGI Global, viewed Feb. 12, 2011). 
650 # 0 |a Systems on a chip  |x Design and construction. 
650 # 0 |a Networks on a chip  |x Design and construction. 
650 # 0 |a Systems on a chip  |x Testing. 
650 # 0 |a Networks on a chip  |x Testing. 
653 # # |a Built-in self repair for logic structures 
653 # # |a Combined test-data compression and test planning 
653 # # |a Diagnostic modeling of digital systems 
653 # # |a Fault simulation and fault injection technology 
653 # # |a Fault-tolerant and fail-safe design based on reconfiguration 
653 # # |a Flexible fault-tolerant schedules for embedded systems 
653 # # |a Memory testing and self-repair 
653 # # |a Optimizing fault tolerance for multi-processor system-on-chip 
653 # # |a Software-based self-test of embedded microprocessors 
653 # # |a Transient faults detection and compensation 
700 1 # |a Ubar, Raimund,  |d 1941- 
700 1 # |a Raik, Jaan,  |d 1972- 
700 1 # |a Vierhaus, Heinrich Theodor,  |d 1951- 
710 2 # |a IGI Global. 
776 0 # |c (Original)  |w (DLC)2010045850 
776 0 8 |i Print version:  |w (DLC) 2010045850  |z 9781609602123  |z 1609602129 
856 4 1 |u https://ezaccess.library.uitm.edu.my/login?url=http://services.igi-global.com/resolvedoi/resolve.aspx?doi=10.4018/978-1-60960-212-3  |3 Chapter PDFs via platform: 

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