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100301s2009 ne | s |||| 0|eng d |
| 020 |
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|a 9781402097577
|9 978-1-4020-9757-7
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|a 10.1007/978-1-4020-9757-7
|2 doi
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|a TK7888.4
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|a 621.3815
|2 23
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|a Murali, Srinivasan.
|e author.
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|a Designing Reliable and Efficient Networks on Chips
|c by Srinivasan Murali.
|h [electronic resource] /
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|a Dordrecht :
|b Springer Netherlands,
|c 2009.
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|b online resource.
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|a text
|b txt
|2 rdacontent
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|a computer
|b c
|2 rdamedia
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|a online resource
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|a text file
|b PDF
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|a Lecture Notes in Electrical Engineering,
|v 34
|x 1876-1100 ;
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| 520 |
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|a Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another important design challenge for NoCs will be to provide dynamic (run-time) support against permanent and intermittent faults that can occur in the system. The purpose of Designing Reliable and Efficient Networks on Chips is to provide state-of-the-art methods to solve some of the most important and time-intensive problems encountered during NoC design.
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|a Engineering.
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|a Computer science.
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|a Systems engineering.
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|a Engineering.
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|a Circuits and Systems.
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|a Processor Architectures.
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|a SpringerLink (Online service)
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|t Springer eBooks
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|i Printed edition:
|z 9781402097560
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| 830 |
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|a Lecture Notes in Electrical Engineering,
|v 34
|x 1876-1100 ;
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| 856 |
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|u https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-1-4020-9757-7
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|a ZDB-2-ENG
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|a Engineering (Springer-11647)
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