Designing Reliable and Efficient Networks on Chips
Developing NoC based interconnect tailored to a particular application domain, satisfying the application performance constraints with minimum power-area overhead is a major challenge. With technology scaling, as the geometries of on-chip devices reach the physical limits of operation, another impor...
| Main Author: | |
|---|---|
| Corporate Author: | |
| Format: | Electronic |
| Language: | English |
| Published: |
Dordrecht :
Springer Netherlands,
2009.
|
| Series: | Lecture Notes in Electrical Engineering,
34 |
| Subjects: | |
| Online Access: | https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-1-4020-9757-7 |