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05948nam a2200541 a 4500 |
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090809s2009 caua fsab 000 0 eng d |
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|a 9781598295856 (electronic bk.)
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|z 9781598295849 (pbk.)
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7 |
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|a 10.2200/S00209ED1V01Y200907CAC008
|2 doi
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|a (CaBNvSL)gtp00535456
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|a CaBNvSL
|c CaBNvSL
|d CaBNvSL
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|a TK5105.546
|b .E575 2009
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|a 004.1
|2 22
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|a Enright Jerger, Natalie D.
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|a On-chip networks
|c Natalie Enright Jerger, Li-Shiuan Peh.
|h [electronic resource] /
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|a San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) :
|b Morgan & Claypool Publishers,
|c c2009.
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| 300 |
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|a 1 electronic text (xii, 127 p. : ill.) :
|b digital file.
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| 490 |
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|a Synthesis lectures on computer architecture,
|v # 8
|x 1935-3243 ;
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| 500 |
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|a Part of: Synthesis digital library of engineering and computer science.
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| 500 |
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|a Title from PDF t.p. (viewed on August 9, 2009).
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|a Series from website.
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|a Includes bibliographical references (p. 105-125).
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|a Introduction -- The advent of the multi-core era -- Communication demands of multi-core architectures -- On-chip vs. off-chip networks -- Network basics: a quick primer -- Evolution to on-chip networks -- On-chip network building blocks -- Performance and cost -- Commercial on-chip network chips -- This book -- Interface with system architecture -- Shared memory networks in chip multiprocessors -- Impact of coherence protocol on network performance -- Coherence protocol requirements for the on-chip network -- Protocol-level network deadlock -- Impact of cache hierarchy implementation on network performance -- Home node and memory controller design issues -- Miss and transaction status holding registers -- Synthesized NoCs in MPSoCs -- The role of application characterization in NoC design -- Design requirements for on-chip network -- NoC synthesis -- NoC network interface standards -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Topology -- Metrics for comparing topologies -- Direct topologies: rings, meshes and Tori -- Indirect topologies: butterflies, Clos networks and fat trees -- Irregular topologies -- Splitting and merging -- Topology synthesis algorithm example -- Layout and implementation -- Concentrators -- Implication of abstract metrics on on-chip implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Routing -- Types of routing algorithms -- Deadlock avoidance -- Deterministic dimension-ordered routing -- Oblivious routing -- Adaptive routing -- Adaptive turn model routing -- Implementation -- Source routing -- Node table-based routing -- Combinational circuits -- Adaptive routing -- Routing on irregular topologies -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Flow control -- Messages, packets, flits and phits -- Message-based flow control -- Circuit switching -- Packet-based flow control -- Store and forward -- Cut-through -- Flit-based flow control -- Wormhole -- Virtual channels -- Deadlock-free flow control -- Escape VCs -- Buffer backpressure -- Implementation -- Buffer sizing for turnaround time -- Reverse signaling wires -- Flow control implementation in MPSoCs -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Router microarchitecture -- Virtual channel router microarchitecture -- Pipeline -- Pipeline implementation -- Pipeline optimizations -- Buffer organization -- Switch design -- Crossbar designs -- Crossbar speedup -- Crossbar slicing -- Allocators and arbiters -- Round-robin arbiter -- Matrix arbiter -- Separable allocator -- Wavefront allocator -- Allocator organization -- Implementation -- Router floorplanning -- Buffer implementation -- Bibliographic notes -- Case studies -- Brief state-of-the-art survey -- Conclusions -- Gap between state-of-the-art and ideal -- Definition of ideal interconnect fabric -- Definition of state-of-the-art -- Network power-delay-throughput gap -- Key research challenges -- Low-power on-chip networks -- Beyond conventional interconnects -- Resilient on-chip networks -- NoC infrastructures -- On-chip network benchmarks -- On-chip networks conferences -- Bibliographic notes.
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|a Abstract freely available; full-text restricted to subscribers or individual document purchasers.
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|a Compendex
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|a INSPEC
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|a Google scholar
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|a Google book search
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|a With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.
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|a Also available in print.
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|a Mode of access: World Wide Web.
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|a System requirements: Adobe Acrobat reader.
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|a Networks on a chip.
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| 690 |
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|a Interconnection networks
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| 690 |
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|a Topology
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| 690 |
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|a Routing
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| 690 |
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|a Flow control
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| 690 |
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|a Computer architecture
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| 690 |
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|a Multiprocessor system on chip
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| 700 |
1 |
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|a Peh, Li-Shiuan.
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|a Synthesis digital library of engineering and computer science.
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|a Synthesis lectures on computer architecture (Online),
|v # 8.
|x 1935-3243 ;
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| 856 |
4 |
2 |
|u https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.2200/S00209ED1V01Y200907CAC008
|3 Abstract with links to full text
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