On-chip networks

• Main Author: Enright Jerger, Natalie D.
• Other Authors: Peh, Li-Shiuan.
• Format: Electronic
• Language: English
• Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009.
• Series: Synthesis lectures on computer architecture (Online), # 8.
• Subjects: Networks on a chip.
• Online Access: Abstract with links to full text
• Item Description: Part of: Synthesis digital library of engineering and computer science.; Title from PDF t.p. (viewed on August 9, 2009).; Series from website.
• Physical Description: 1 electronic text (xii, 127 p. : ill.) : digital file.; Also available in print.
• Format: Mode of access: World Wide Web.; System requirements: Adobe Acrobat reader.
• Bibliography: Includes bibliographical references (p. 105-125).
• ISBN: 9781598295856 (electronic bk.)
• ISSN: 1935-3243
• Access: Abstract freely available; full-text restricted to subscribers or individual document purchasers.

With the ability to integrate a large number of cores on a single chip, research into on-chip networks to facilitate communication becomes increasingly important. On-chip networks seek to provide a scalable and high-bandwidth communication substrate for multi-core and many-core architectures. High bandwidth and low latency within the on-chip network must be achieved while fitting within tight area and power budgets. In this lecture, we examine various fundamental aspects of on-chip network design and provide the reader with an overview of the current state-of-the-art research in this field.