Chip multiprocessor architecture techiniques to improve throughput and latency /

• Main Author: Olukotun, Kunle.
• Other Authors: Hammond, Lance., Laudon, James.
• Format: Electronic
• Language: English
• Published: San Rafael, Calif (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, 2007.
• Edition: 1st ed.
• Series: Synthesis lectures on computer architecture (Online) ; #3.
• Subjects: Parallel processing (Electronic computers); High performance processors.; Computer architecture.
• Online Access: Abstract with links to full text
• Item Description: Part of: Synthesis digital library of engineering and computer science.; Title from PDF t.p. (viewed on Nov. 7, 2008).; Series from website.
• Physical Description: 1 electronic text (viii, 145 p. : ill.) : digital file.; Also available in print.
• Format: Mode of access: World Wide Web.; System requirements: Adobe Acrobat Reader.
• Bibliography: Includes bibliographical references.
• ISBN: 9781598291230 (electronic bk.); 1598291238 (electronic bk.); 9781598291124 (pbk.); 159829122x (pbk.)
• ISSN: 1935-3243
• Access: Abstract freely available; full-text restricted to subscribers or individual document purchasers.

Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two.