Power Aware Design Methodologies

Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion...

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Bibliographic Details
Corporate Author: SpringerLink (Online service)
Other Authors: Pedram, Massoud. (Editor), Rabaey, Jan M. (Editor)
Format: Electronic
Language:English
Published: Boston, MA : Springer US, 2002.
Subjects:
Online Access:View fulltext via EzAccess
LEADER 03362nam a22004455i 4500
001 23252
003 DE-He213
005 20151204162621.0
007 cr nn 008mamaa
008 100301s2002 xxu| s |||| 0|eng d
020 # # |a 9780306481390  |9 978-0-306-48139-0 
024 7 # |a 10.1007/b101914  |2 doi 
050 # 4 |a TK7888.4 
072 # 7 |a TJFC  |2 bicssc 
072 # 7 |a TEC008010  |2 bisacsh 
082 0 4 |a 621.3815  |2 23 
245 1 0 |a Power Aware Design Methodologies  |c edited by Massoud Pedram, Jan M. Rabaey.  |h [electronic resource] / 
264 # 1 |a Boston, MA :  |b Springer US,  |c 2002. 
300 # # |a XX, 522 p.  |b online resource. 
336 # # |a text  |b txt  |2 rdacontent 
337 # # |a computer  |b c  |2 rdamedia 
338 # # |a online resource  |b cr  |2 rdacarrier 
347 # # |a text file  |b PDF  |2 rda 
505 0 # |a CMOS Device Technology Trends for Power-Constrained Applications -- Low Power Memory Design -- Low-Power Digital Circuit Design -- Low Voltage Analog Design -- Low Power Flip-Flop and Clock Network Design Methodologies in High-Performance System-on-a-Chip -- Power Optimization by Datapath Width Adjustment -- Energy-Efficient Design of High-Speed Links -- System and Microarchitectural Level Power Modeling, Optimization, and Their Implications in Energy Aware Computing -- Tools and Techniques for Integrated Hardware-Software Energy Optimizations -- Power-Aware Communication Systems -- Power-Aware Wireless Microsensor Networks -- Circuit and System Level Power Management -- Tools and Methodologies for Power Sensitive Design -- Reconfigurable Processors Ớ The Road to Flexible Power-Aware Computing -- Energy-Efficient System-Level Design. 
520 # # |a Power Aware Design Methodologies was conceived as an effort to bring all aspects of power-aware design methodologies together in a single document. It covers several layers of the design hierarchy from technology, circuit logic, and architectural levels up to the system layer. It includes discussion of techniques and methodologies for improving the power efficiency of CMOS circuits (digital and analog), systems on chip, microelectronic systems, wirelessly networked systems of computational nodes and so on. In addition to providing an in-depth analysis of the sources of power dissipation in VLSI circuits and systems and the technology and design trends, this book provides a myriad of state-of-the-art approaches to power optimization and control. The different chapters of Power Aware Design Methodologies have been written by leading researchers and experts in their respective areas. Contributions are from both academia and industry. The contributors have reported the various technologies, methodologies, and techniques in such a way that they are understandable and useful. 
650 # 0 |a Engineering. 
650 # 0 |a Electrical engineering. 
650 # 0 |a Electronic circuits. 
650 1 4 |a Engineering. 
650 2 4 |a Circuits and Systems. 
650 2 4 |a Electrical Engineering. 
700 1 # |a Pedram, Massoud.  |e editor. 
700 1 # |a Rabaey, Jan M.  |e editor. 
710 2 # |a SpringerLink (Online service) 
773 0 # |t Springer eBooks 
776 0 8 |i Printed edition:  |z 9781402071522 
856 4 0 |u https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/b101914  |z View fulltext via EzAccess 
912 # # |a ZDB-2-ENG 
912 # # |a ZDB-2-BAE 
950 # # |a Engineering (Springer-11647)