Pipelined ADC Design and Enhancement Techniques

Pipelined ADCs have seen phenomenal improvements in performance over the last few years. As such, when designing a pipelined ADC a clear understanding of the design tradeoffs, and state of the art techniques is required to implement today's high performance low power ADCs. Written for both rese...

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Bibliographic Details
Main Author: Ahmed, Imran. (Author)
Corporate Author: SpringerLink (Online service)
Format: Electronic
Language:English
Published: Dordrecht : Springer Netherlands, 2010.
Series:Analog Circuits and Signal Processing
Subjects:
Online Access:https://ezaccess.library.uitm.edu.my/login?url=http://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-90-481-8652-5
Table of Contents:
  • Chapter 1: Introduction
  • SECTION I: PIPELINED ADC DESIGN. Chapter 2: ADC Architectures. Chapter 3: Pipelined ADC Architecture Overview. Chapter 4: Scaling Power with Sampling rate in an ADC. Chapter 5: State of the art Pipelined ADC Design
  • SECTION II: PIPELINED ADC ENHANCEMENT TECHNIQUES. Chapter 6: Rapid calibration of DAC and gain errors in a multi-bit pipeline stage. Chapter 7: A Power Scalable and Low Power Pipelined ADC. Chapter 8: A sub-sampling ADC with embedded sample-and-hold. Chapter 9: A capacitive charge pump based low power pipelined ADC. Chapter 10: Summary
  • References. Index.