Verification and Validation in Systems Engineering Assessing UML/SysML Design Models /

• Main Authors: Debbabi, Mourad. (Author), Hassan̐e, Fawzi. (Author), Jarraya, Yosr. (Author), Soeanu, Andrei. (Author), Alawneh, Luay. (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic
• Language: English
• Published: Berlin, Heidelberg : Springer Berlin Heidelberg, 2010.
• Subjects: Computer science.; Computer system performance.; Software engineering.; Information Systems.; Computer Science.; Software Engineering.; System Performance and Evaluation.; Management of Computing and Information Systems.
• Online Access: https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-3-642-15228-3

Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be...

Table of Contents:

• 1 Introduction
• 2 Architecture Frameworks and Model-Driven Simulation
• 3 Unified Modeling Language
• 4 Systems Modeling Language
• 5 Verification, Validation and Accreditation
• 6 Automatic Approach for Synergistic Verification and Validation
• 7 Software Engineering Metrics in the Context of Systems Engineering
• 8 Verification and Validation of UML Behavioral Diagrams
• 9 Probabilistic Model-Checking of SysML Activity Diagrams
• 10 Performance Analysis of Time Constrained SysML Activity Diagrams
• 11 Semantic Foundations of SysML Activity Diagrams
• 12 Soundness of the Translation Algorithm
• 13 Conclusion. Index.