Verification and Validation in Systems Engineering Assessing UML/SysML Design Models /
Verification and validation represents an important process used for the quality assessment of engineered systems and their compliance with the requirements established at the beginning of or during the development cycle. Debbabi and his coauthors investigate methodologies and techniques that can be...
| Main Authors: | , , , , |
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| Corporate Author: | |
| Format: | Electronic |
| Language: | English |
| Published: |
Berlin, Heidelberg :
Springer Berlin Heidelberg,
2010.
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| Subjects: | |
| Online Access: | https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-3-642-15228-3 |