Minimizing and Exploiting Leakage in VLSI Design

• Main Authors: Jayakumar, Nikhil. (Author), Paul, Suganth. (Author), Garg, Rajesh. (Author), Gulati, Kanupriya. (Author), Khatri, Sunil P. (Author)
• Corporate Author: SpringerLink (Online service)
• Format: Electronic
• Language: English
• Published: Boston, MA : Springer US, 2010.
• Subjects: Engineering.; Computer aided design.; Systems engineering.; Circuits and Systems.; Computer-Aided Engineering (CAD, CAE) and Design.
• Online Access: https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-1-4419-0950-3

Minimizing and Exploiting Leakage in VLSI Design Nikhil Jayakumar, Suganth Paul, Rajesh Garg, Kanupriya Gulati and Sunil P. Khatri Power consumption of VLSI (Very Large Scale Integrated) circuits has been growing at an alarmingly rapid rate. This increase in power consumption, coupled with the incre...

Table of Contents:

• Introduction
• Minimizing Leakage in Modern Day DSM Processes
• Existing Leakage Minimizing Approaches
• Computing Leakage Current Distributions
• Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Possibilities
• The HL Approach-A Low-Leakage ASIC Design Methodology
• Simultaneous Input Vector Control and Circuit Modification
• Optimum Reverse Body Biasing for Leakage Minimization
• Exploiting Leakage Through Sub-threshold Circuit Design
• Adaptive Body Biasing to Compensate for PVT Variations
• Optimum VDD for Minimum Energy
• Reclaiming the Sub-threshold Speed Penalty Through Micropipelining
• Design of a Sub-threshold BFSK Transmitter IC
• Design of the Chip
• Implementation of the Chip
• Experimental Results
• Summary and Future Work
• Conclusion.