|
|
|
|
| LEADER |
03762nam a22005055i 4500 |
| 001 |
5207 |
| 003 |
DE-He213 |
| 005 |
20130725190502.0 |
| 007 |
cr nn 008mamaa |
| 008 |
100301s2009 ne | s |||| 0|eng d |
| 020 |
# |
# |
|a 9781402093654
|9 978-1-4020-9365-4
|
| 024 |
7 |
# |
|a 10.1007/978-1-4020-9365-4
|2 doi
|
| 050 |
# |
4 |
|a TK7888.4
|
| 072 |
# |
7 |
|a TJFC
|2 bicssc
|
| 072 |
# |
7 |
|a TEC008010
|2 bisacsh
|
| 082 |
0 |
4 |
|a 621.3815
|2 23
|
| 100 |
1 |
# |
|a Chang, Kai-hui.
|e author.
|
| 245 |
1 |
0 |
|a Functional Design Errors in Digital Circuits
|b Diagnosis, Correction and Repair /
|c by Kai-hui Chang, Igor L. Markov, Valeria Bertacco.
|h [electronic resource] :
|
| 264 |
# |
1 |
|a Dordrecht :
|b Springer Netherlands,
|c 2009.
|
| 300 |
# |
# |
|b online resource.
|
| 336 |
# |
# |
|a text
|b txt
|2 rdacontent
|
| 337 |
# |
# |
|a computer
|b c
|2 rdamedia
|
| 338 |
# |
# |
|a online resource
|b cr
|2 rdacarrier
|
| 347 |
# |
# |
|a text file
|b PDF
|2 rda
|
| 490 |
1 |
# |
|a Lecture Notes in Electrical Engineering,
|v 32
|x 1876-1100 ;
|
| 505 |
0 |
# |
|a Dedication. List of Figures. List of Tables. Preface -- Part I Background and Prior Art. 1. Introduction. 2. Current Landscape in Design and Verification. 3. Finding Bugs and Repairing Circuits -- Part II FogClearMethodologies and Theoretical Advances in Error Repair. 4. Circuit Design and Verification Methodologies. 5. Counterexample-Guided Error-Repair Framework. 6. Signature-Based Resynthesis Techniques. 7. Symmetry-Based Rewiring -- Part III FogClear Components. 8. Bug Trace Minimization. 9. Functional Error Diagnosis and Correction. 10. Incremental Verification for Physical Synthesis. 11. Post-Silicon Debugging and Layout Repair. 12. Methodologies for Spare-Cell Insertion. 13. Conclusions -- Index. References.
|
| 520 |
# |
# |
|a Due to the dramatic increase in design complexity, modern circuits are often produced with functional errors. While improvements in verification allow engineers to find more errors, fixing these errors remains a manual and challenging task. Functional Design Errors in Digital Circuits Diagnosis covers a wide spectrum of innovative methods to automate the debugging process throughout the design flow: from Register-Transfer Level (RTL) all the way to the silicon die. In particular, this book describes: (1) techniques for bug trace minimization that simplify debugging; (2) an RTL error diagnosis method that identifies the root cause of errors directly; (3) a counterexample-guided error-repair framework to automatically fix errors in gate-level and RTL designs; (4) a symmetry-based rewiring technology for fixing electrical errors; (5) an incremental verification system for physical synthesis; and (6) an integrated framework for post-silicon debugging and layout repair. In addition, Functional Design Errors in Digital Circuits Diagnosis describes a comprehensive evaluation of spare-cell insertion methods. The solutions provided in this book can greatly reduce debugging effort, enhance design quality, and ultimately enable the design and manufacture of more reliable electronic devices.
|
| 650 |
# |
0 |
|a Engineering.
|
| 650 |
# |
0 |
|a Logic design.
|
| 650 |
# |
0 |
|a Computer aided design.
|
| 650 |
# |
0 |
|a Systems engineering.
|
| 650 |
1 |
4 |
|a Engineering.
|
| 650 |
2 |
4 |
|a Circuits and Systems.
|
| 650 |
2 |
4 |
|a Computer-Aided Engineering (CAD, CAE) and Design.
|
| 650 |
2 |
4 |
|a Logic Design.
|
| 700 |
1 |
# |
|a Markov, Igor L.
|e author.
|
| 700 |
1 |
# |
|a Bertacco, Valeria.
|e author.
|
| 710 |
2 |
# |
|a SpringerLink (Online service)
|
| 773 |
0 |
# |
|t Springer eBooks
|
| 776 |
0 |
8 |
|i Printed edition:
|z 9781402093647
|
| 830 |
# |
0 |
|a Lecture Notes in Electrical Engineering,
|v 32
|x 1876-1100 ;
|
| 856 |
4 |
0 |
|u https://ezaccess.library.uitm.edu.my/login?url=http://dx.doi.org/10.1007/978-1-4020-9365-4
|
| 912 |
# |
# |
|a ZDB-2-ENG
|
| 950 |
# |
# |
|a Engineering (Springer-11647)
|