Cover Image

Asynchronous sequential machine design and analysis a comprehensive development of the design and analysis of clock-independent state machines and systems /

Asynchronous Sequential Machine Design and Analysis provides a lucid, in-depth treatment of asynchronous state machine design and analysis presented in two parts: Part I on the background fundamentals related to asynchronous sequential logic circuits generally, and Part II on self-timed systems, hig...

Full description

Bibliographic Details
Main Author: Tinder, Richard F., 1930-
Format: Electronic
Language:English
Published: San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, c2009.
Series:Synthesis lectures on digital circuits and systems (Online) ; # 18.
Subjects:
Asynchronous circuits > Mathematical models.
Sequential circuits > Mathematical models.
Sequential machine theory > Mathematical models.
Online Access:View fulltext via EzAccess
Table of Contents:
  • Background fundaments for design and analysis of asynchronous state machines
  • Introduction and background
  • Features of and need for asynchronous finite state machines
  • Fundamental mode of operation and lumped path delay models
  • Stability criteria and the excitation table for LPD models
  • Nested set-reset element models for asynchronous sequential machines
  • Fully documented state diagram, sum rule and mutually exclusive requirement
  • The mapping algorithm
  • Application of the mapping algorithm to simple LPD model designs
  • Mixed-logic notation and the cardinal rule
  • Design of basic memory elements and their characteristics
  • Basic SR cells
  • Muller C-elements
  • Summary of the excitation tables
  • Huffman vs. Muller asynchronous FSMs
  • Simple FSM design and initialization
  • The extended Y-SR mapping algorithm
  • Application to FSM design with C-elements
  • Initialization of asynchronous FSMs
  • Sanity circuits, design and applications
  • Detection and elimination of timing defects in asynchronous FSMs
  • Endless cycles
  • Races and critical races
  • Static hazards in the NS and output forming logic
  • Detection and elimination of static hazards in the NS forming logic
  • Detection and elimination of static hazards in the output forming logic
  • Dynamic hazards and function hazards
  • Output race glitches, detection and elimination
  • Essential hazards, detection and elimination
  • Minimum requirements for E-hazard and D-trio formation
  • A simple example
  • Metastable conditions in C-elements
  • Design of single transition time machines
  • The array algebraic approach
  • Design example using C-elements
  • Essential hazard analysis in STT FSMs
  • Computer aided STT FSM design
  • Summary of hazard effects and their elimination in STT FSM designs
  • Design of one-hot asynchronous FSMs
  • Introduction to the one-hot approach
  • Characteristics of the one-hot method
  • Design example using C-elements
  • Essential hazards in one-hot asynchronous FSMs
  • Design of pulse mode FSMs
  • Models and characteristics of the pulse mode
  • Requirements and characteristics of the pulse mode approach
  • Toggle modules as the memory elements
  • A design example
  • Other memory elements suitable for pulse mode design
  • Debouncing circuits
  • Analysis of asynchronous FSMs
  • Procedure for analyzing any asynchronous FSM
  • Example of an LPD model FSM analysis
  • E-hazard and D-trio analyses of the PGM
  • Example of an STT FSM analysis
  • Example of a one-hot FSM analysis
  • Example of a pulse mode FSM analysis
  • Self-timed systems, programmable sequencers, and arbiters
  • Externally asynchronous/internally clocked systems
  • Basic architecture and system characteristics
  • DFLOP memory element design with C-elements
  • D-trio analysis of the resolver FSM
  • Simple example of an EAIC FSM design
  • The metastable detection stage
  • Frequency characteristics and NS logic constraints of EAIC systems
  • Parallel/serial processing with cascaded EAIC microcontrollers
  • Characteristics
  • Summary of the salient features of EAIC systems
  • Cascadable asynchronous programmable sequencers (CAPS) and time-shared system design
  • Microprogrammable asynchronous controller modules
  • MAC module characteristics for use with CAPS system architecture
  • C-element design of a 2 x 2 MAC module
  • Stepwise operation of the MAC module
  • Cascading the MAC modules
  • Programming the MAC module, four examples
  • Time-shared FSM operation by using cascaded MAC modules
  • Asynchronous one-hot programmable sequencer systems
  • General architecture
  • Design of one-hot sequencers
  • Time-shared multiple FSM operation by a single A-OPS
  • A-OPS software capabilities used in this text
  • Arbiter modules
  • Bus arbiter module
  • Multiple input bus arbiters
  • Priority stand-alone arbiters
  • Handshake arbiters with acknowledgment (done) signals
  • Rotating token arbiters
  • Applications
  • Appendix A
  • Brief reviews
  • A.1 Mixed-logic gate symbology and conjugate gate forms
  • A.2 And/or laws and the EQV/XOR laws of Boolean algebra (dual relations)
  • A.3 Entered variable K-map compression and minimization
  • A.3.1 Incompletely specified functions
  • Appendix B End-of-chapter problems
  • Endnotes
  • General background directly supporting material in this text
  • Alternative approaches to asynchronous state machine design and analysis
  • Important historical contributions to asynchronous circuit synthesis
  • Sources related to the subject of EAIC systems discussed in this text
  • Glossary of terms, expressions, and abbreviations
  • Author biography
  • Index.

Similar Items