Computer architecture techniques for power-efficiency

• Main Author: Kaxiras, Stefanos.
• Other Authors: Martonosi, Margaret.
• Format: Electronic
• Language: English
• Published: San Rafael, Calif (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, 2008.
• Edition: 1st ed.
• Series: Synthesis lectures on computer architecture (Online) ; #4.
• Subjects: Computer architecture.; Mechanical efficiency.
• Online Access: Abstract with links to full text

 In the last few years, power dissipation has become an important design constraint, on par with performance, in the design of new computer systems. Whereas in the past, the primary job of the computer architect was to translate improvements in operating frequency and transistor count into performance, now power efficiency must be taken into account at every step of the design process. While for some time, architects have been successful in delivering 40% to 50% annual improvement in processor performance, costs that were previously brushed aside eventually caught up. The most critical of these costs is the inexorable increase in power dissipation and power density in processors. Power dissipation issues have catalyzed new topic areas in computer architecture, resulting in a substantial body of work on more power-efficient architectures. Power dissipation coupled with diminishing performance gains, was also the main cause for the switch from single-core to multi-core architectures and a slowdown in frequency increase.